1. Field of the Invention
This invention relates to the packaging of semiconductor devices, and in particular to methods and apparatus for increasing the routing density of a ball grid array package, a printed wiring board or the like.
2. Description of the Related Art
As pin counts of chips increase, there is a concomitant need for packages that can connect these greater numbers of output leads to a printed wiring board (PWB). Similarly, there is a need for PWB's with increased routing density, especially considering the trend toward smaller and smaller devices (e.g. cell phones); for a given surface area of PWB, it is desirable to route as many wires as possible.
FIG. 1 shows a typical two surface routing scheme for a PWB. As shown, a plurality of ball pads 10 serves to electrically couple a PWB 12 with a plurality of solder balls 14 on a ball grid array (BGA) package 16. The PWB comprises a substrate with two surfaces, 18 and 20, which are located on first and second planes, 19 and 21, which are parallel to one another. The plurality of ball pads 10 are on surface 18. A first group 20 of the plurality of ball pads 10 is routed by traces 22 on surface 18 while a second group 24 of the plurality of ball pads 10 is routed by traces 26 on surface 20. Each of a plurality of short traces 29 (see FIG. 2a) electrically couples a corresponding one of the second group 24 with a corresponding one of a plurality of vias 28, which in turn is connected to a corresponding one of the traces 26 on surface 20.
As can be seen by referring to FIGS. 2a and 2b, spacing constraints between traces prevent all the plurality of solder ball pads 10 from being routed on the same surface; thus, the two (or more) level routing scheme is required for the that is routed as shown in FIGS. 2a and 2b. FIG. 2a shows the routing scheme for surface 18 while FIG. 2b shows the routing scheme for surface 20. As shown in FIG. 2a, the distance between the traces 22 must exceed a certain threshold. (The same holds true for the traces 26 in FIG. 2b). Therefore, given the area of surface 18, the second group of ball pads 24 could not be routed on surface 18. Instead, each of the vias 28 connects one of the second group of ball pads 24 to the traces 26 on surface 20. The vias 28 are arranged in a grid like structure; that is, the orientation between each of the vias 28 and its respective ball pad is constant.
For a printed circuit board (or substrate etc.) with a given surface area, it is desirable to increase, relative to the scheme shown in FIG. 1, the number of ball pads (or solder balls etc.) that can be routed.